//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_PIC_H__
#define __ELASTOS_PIC_H__

// Registers' IO address
#define _ICCR   ((ioport_t)0x80d00014)  // Control Register
#define _ICLR   ((ioport_t)0x80d00008)  // Level Register1
#define _ICLR2  ((ioport_t)0x80d000a4)  // Level Register2
#define _ICMR   ((ioport_t)0x80d00004)  // Mask Register1
#define _ICMR2  ((ioport_t)0x80d000a0)  // Mask Register2
#define _ICIP   ((ioport_t)0x80d00000)  // IRQ Pending Register1
#define _ICIP2  ((ioport_t)0x80d0009c)  // IRQ Pending Register2

// End-of-Interrupt Registers
//#define _TCEOI1     ((ioport_t)0x80000c0c)
//#define _TCEOI2     ((ioport_t)0x80000c2c)
//#define _TCEOI3     ((ioport_t)0x80000c8c)

// ICCR
#define _DIM    __32BIT(0)

#endif // __ELASTOS_PIC_H__
